Author Topic: Gated Pulse Frequency Generator Schematic  (Read 35410 times)

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Re: Gated Pulse Frequency Generator Schematic
« Reply #16 on: March 28, 2011, 04:16:25 am »
here is a screenshot of the results

filename should be 4538...ignore filename...contents are correct
« Last Edit: March 28, 2011, 06:53:20 am by ali »

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Re: Gated Pulse Frequency Generator Schematic
« Reply #17 on: March 28, 2011, 04:26:56 am »
I simply use the ne555 and the lm741 for the pulse width and frequency adjustable gate generator.. Like in my diagram, work very nice...

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Re: Gated Pulse Frequency Generator Schematic
« Reply #18 on: March 28, 2011, 05:04:08 am »
Here's the schematic for the gating signal.
There is some bleed through from the back of the sheet,but it's still readable.Someone can do a better job with MS Paint or whatever (TONY)
Don

thanks for all you are doing. Please help with this one sir. the schematic you posted does not simulate with the component values given
attached is a multisim 11 file to show exactly what i mean, here is your circuit for you to simulate (attached)

i believe a CD 4538 will work better with a slightly different configuration for the circuit ( i posted  it in another section of this topic)
thANKS AGAIN!

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Re: Gated Pulse Frequency Generator Schematic
« Reply #19 on: March 28, 2011, 05:20:03 am »
Don,
Can you post an actual image of just the gated circuit section?

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Re: Gated Pulse Frequency Generator Schematic
« Reply #20 on: March 28, 2011, 22:25:42 pm »
Tony, vee is usually a negative value if you go by the definition.In figure 5 vee was +12 volts.When Stan used 10 volts anywhere he labeled it that way as you pointed out.VEE in figure 6 just powers the ligh,no big deal there.I don't have an image for this schematic.
 
Ali,the signal coming into firgure 6 is from the Digital Control Means when in auto mode,and the Variable Pulse Frequency Generator when on manual.When in manual mode it will be a square wave 50% duty cycle signal.I have no idea why it won't work in your simulator, don't have alot of faith in them when it comes to Stans work.
 
The schematic is correct,it's how it was on the board.Tony pointed out a wrong value for one of the resistors in the schematic I posted,did you make that adjustment to you sim?
 
Don
 
 

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Re: Gated Pulse Frequency Generator Schematic
« Reply #21 on: March 28, 2011, 23:17:58 pm »
oh ok thanks...yea typically VEE is a negative voltage but I don't see where that would work in this setup. It could just be a typo.

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Re: Gated Pulse Frequency Generator Schematic
« Reply #22 on: March 29, 2011, 01:01:02 am »
Tony, vee is usually a negative value if you go by the definition.In figure 5 vee was +12 volts.When Stan used 10 volts anywhere he labeled it that way as you pointed out.VEE in figure 6 just powers the ligh,no big deal there.I don't have an image for this schematic.
 
Ali,the signal coming into firgure 6 is from the Digital Control Means when in auto mode,and the Variable Pulse Frequency Generator when on manual.When in manual mode it will be a square wave 50% duty cycle signal.I have no idea why it won't work in your simulator, don't have alot of faith in them when it comes to Stans work.
 
The schematic is correct,it's how it was on the board.Tony pointed out a wrong value for one of the resistors in the schematic I posted,did you make that adjustment to you sim?
 
Don

when i was able to massage the components to make the specified circuit figure 6 work, the triggering went from 10% duty cycle to 50% and then gradually back towards 10%... even though the figure 2 signal was going from 10% towards 90%
???
so i came up with a better alternative that will work with up to 20 VDC that simulates correctly.
I will wait to see if anyone builds the 74122 version and then post my actual scope results from my cd4538 version

as long as the end result is the same who cares what the schematic or components are.

Don have you tried running both simulations i posted?

Also Don, what frequency range are we shooting for on the variable pulse freq. gen fig 12  ?
will the fact that there are divide by 2 chips on FIG 12 cause a perfect 50% duty cycle, becausecause those 555 timers are terrible on their waveform for output

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Re: Gated Pulse Frequency Generator Schematic
« Reply #23 on: March 29, 2011, 02:00:14 am »
Ali,
I don't have the copy of that simulator,so I haven't tried to run them.I don't care to either.I was able to test that original circuit,and it worked just fine.
 
The frequency generator should go to 40khz out of the 555 before going into the 4017.
Any duty cycle into those 4017 chips will always come out at 50% duty cycle.That's what they do along with the devide by function.
 
Don