Author Topic: Gated Pulse Frequency Generator Schematic  (Read 35405 times)

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Re: Gated Pulse Frequency Generator Schematic
« Reply #8 on: March 28, 2011, 00:43:14 am »
ok thanks Don =)

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Re: Gated Pulse Frequency Generator Schematic
« Reply #9 on: March 28, 2011, 01:49:04 am »
Thanks Don! Hit us with the next quiz :)

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Re: Gated Pulse Frequency Generator Schematic
« Reply #10 on: March 28, 2011, 02:54:36 am »
Don,
Did Stan make any reference to what VEE is? Is it maybe an unregulated voltage, regulated voltage, extra smoothed voltage, variable voltage?

« Last Edit: March 28, 2011, 03:20:27 am by sebosfato »

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Re: Gated Pulse Frequency Generator Schematic
« Reply #11 on: March 28, 2011, 03:22:30 am »
Don,
Did Stan make any reference to what VEE is? Is it maybe an unregulated voltage, regulated voltage, extra smoothed voltage, variable voltage?
Tony sorry i erroneously edited your post, while trying to quote...



Here's something i wanted to know too.

By the way,
Thanks for everything Don.


Br
sebs

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Re: Gated Pulse Frequency Generator Schematic
« Reply #12 on: March 28, 2011, 03:36:43 am »
Also I would like to add, could VEE maybe be 10v cuz on Stan's GMS he has an indicator light for 10v and also on some of the components in the patent he has them powered by 10v such as in fig. 11 and fig. 8.

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Re: Gated Pulse Frequency Generator Schematic
« Reply #13 on: March 28, 2011, 03:52:53 am »
just spent the last 4 hours trying to simulate dons post of the figure 6 schematic in multisim
No Luck, it does not do what we want...maybe those NOR chips were XNOR or AND on the input???

anyway i got to thinking on this and multisim has a retriggerable monostable multivubrator in the CD series
CD4058

so i found that if we want an output that has a gate of variable width inside of a variable duty cycle from the accelerator we cant just trigger the 74122 or 74123 with the high logic signal it doesnt work...

but this circuit here does work, only change is get rid of those logic components on the input and we keep the safety pull ring to turn it off in emergency...but the most important part is figure 12

if we feed this CD 4058 with one signal from the figure 12 ckt to trigger the gate at say 5khz
and then send that 5 khz to the figure 2 manual PWM
we get what we want

an accelerator pedal on top of a gate that is manually adjustable on top of a PLL frequency just like the normal output of fig 6 ties into the pll ay point "A"

here it is:

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Re: Gated Pulse Frequency Generator Schematic
« Reply #14 on: March 28, 2011, 04:03:33 am »
wow i been try in to put that into multism too  lol  im not good at that stuff.

what is it listed as cuz i cant find it?

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Re: Gated Pulse Frequency Generator Schematic
« Reply #15 on: March 28, 2011, 04:15:04 am »
search like this    *74123*