My pll circuit

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I completed the pll circuit... I just decided to not construct the scanning because there was no space left at my solder less breadboard... with the oscilloscope i could determine the functioning of the lock in indicator and feed back circuit...

The lock in led will light if the phases between the signals coming from pin 1 and 2 from the cd4046 are within the range determined by the capacitor at the lock in circuit. this used the 74 002 nor gates 5volts chips... high speed !

The pulse indicator circuit need a high speed op-amp to be able to add as little phase delay as possible to the feedback signal. Here according to the analysis that tony made from the vic, he seem to have used the nte918

I wired the output of the pll to a not gate and connected to the pulse indicator to determine this... up to around 7 khz the ua741 op-amp still lock in...

I will get the better components to test it..

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I couldn't find the nte or ecg 918 opamp at my electronic parts supplier so i'm going to use instead the LM318 that has similar  slew rates high speed capabilities...

I guess this new circuit will lock in up to more several kilohertz since it wont add up much phase delay to the feed back signal.

Stan didn't wired up the output pin four of the pll straight to pin 3... why.. to add some delay to the line in such way to allow for the signal from the feed back be able to lock in at greater frequencies...  I would guess... this delay caused by the driver circuit, the stages of transistors adds maybe up to 100ns or more delay to the signal... so the feedback phase delay problem that arise with increasing frequency can be minimized... 

Now is clear why circuits i did in the past wasn't able to lock in at higher frequency i was using the lm741 opamps like... as i didn't had a good oscilloscope i could not see this differences clearly... nor i knew much about all this at the time i started playing with it.

With the pll stabilized the signal become really clean...

PLL's are used for generating highly stable frequency and is able to modulate it with low noise if properly setup.

hope you enjoy this info...

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I read more about pll's to understand better how this lock in indicator circuit works...

I found that the led will light brightly when the signal coming from the pll pin 1 is dc, this means there is no phase difference between the signal going into pins 3 and 14...

The diode and resistor combination allow the capacitor at the lock in circuit to get charged in a small time if out of lock happens and take more time to discharge... so only when its discharged there is a lock indication...

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If the feedback signal comes from a coil in the vic transformer it will tend to tune in to the self resonance of the vic coils inductance capacitance... not a resonance of a resonant circuit.. i guess thats why stan uses so small signal transistors...

That being the case the inductor becomes a high impedance to the flow of amps as more amps develops more volts at resonance... Its should behave like a line transmission, with distribute capacitance and inductances... like many parallel tanks in series.

if this is the case the resonance across each turn will add up volts together... as the coils are not perfectly arranged theres not only one resonance frequency there is one that is central dominant because the inductors compensate as they are a series coupled inductors...

Once i got this effect unfortunately at that time the transformer wasn't connected properly to the cell and it burned into a blue fire... i was using steel coil that was covered with a black insulation like.

The pll was tuned manually to the frequency, without any feedback... probably the material of the wire helped because widened the bandwidth...

it was october 2008 if i remember well...

I thought this snubber circuit to be able to stop burning the switches... i have no money left for them ha..

notice that as the capacitor try to charge with greater voltage than source voltage the diodes allow the capacitor to be charged to a safe voltage and be discharged thru the coil during the switch on time, making use of some of this wasted energy... another switch could be added to allow the pulse to collapse all into the capacitor than direct it across the coil... a diode in series with the dc source will prevent the recharging effect protecting the source...

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very efficient design!

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Although i designed my own gate circuit to gate the pll, i was curious to understand better why meyer did things the way he did, so i started to take a look into how he generated the gate signal and why principally.

He uses a 555 timer and a set of frequency dividers 1/10, this means the range of precision of frequency is higher at lower frequencies.

He than uses a simple circuit that allows him to create a small pulse proportional to this clock signal, this short pulse goes to the 74ls122 chip which than generates the gate duty cycle adjustment from this small pulse length to 100%

the circuit that creates the short pulses is this:

ps the bigger the capacitor the bigger is the time to turn on, and the wider is the shortest pulse.. remember the pulse is proportional to frequency, given its a kind of RC network...




A stable gate frequency could be useful if we instead of using the pll as a frequency generator we use it as a pulse modulator...

I mean it can also work as a frequency multiplier i found at a book, so it can generates harmonics of a fundamental frequencies, instead of usual use as sub harmonic generator...

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 I'm looking into my pll frequency follower...

 Its now able to follow another frequency source but a bit lossy i'm improving it...

I found that maybe the pulse indicator circuit was wrong designed on stans schematics because it wasn't turning off the lights if theres no pulse detected... I fixed it inverting the inputs... I mean where the 5v signal goes to.

Thats why i have my doubts if is good or no to take a board ready from someone for example... since they are based on copy not design... at least it seems to me...

If you connect a 5 v to the + side of the opamp and the signal is not coming to the neg. input , the led still light because the output of the opamp will be positive...  of course!

referring to the diagram in attachment...

in the patent indeed both inputs are brought to same potential vdd... 

I'm also thinking about use active filtering this way better and faster lock in can be assured... all it takes is another opamp wired as voltage follower connected from pin 13 to 9... this enhances the ability of the phase comparator to charge or discharge the filter capacitor... 

I'm using only a manual adjustment of the frequency, so i added a 200k pot between the voltage divider signal setting the frequency and pin 9 this way if the system is close to resonance the impedance is high enough for the pll to take place regulating the filters voltage.

If no signal is detected the frequency goes to a minimum according to 4046 datasheets if using the phase comparator 2...

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Yet about this diagram the signal going thru a 22kohm resistor at the primary going straight to the pin 3 of the pll might also be wrong, except a zener diode is added, in the place or in parallel with that 10pf capacitor to prevent over voltages... otherwise if you put power into the circuit the  pll chip  could burns...  I guess the best option is to take this signal from the base of the last transistor...