I have a question about this schematic, Tony and others.. .
Why would you want a delayed signal getting into the Pll pin 3 which is the phase comparator input?
Being this way is understandable the damper resistor and diode in parallel with the primary...
Did you found any special reason for that?
I'm meaning pin 4 generates the positive so it turns off the first transistor pnp this turns off all the other transistors and so than makes a positive signal going into pin 3...
Don't you think it can give any kind of delay in the phase causing slightly lower frequency than resonance to be applied?
Or could it be to softening the signal?
I wire straight from pin 4 to 3 just like in the patent shows.
I simplified also the gated pulse frequency generator i use only 555 and 741 as in my schematic instead of 8 ics... it goes from 0 up to 100% duty cycle.
My pll system has only 8 ics including the transistor driver...
Nor i use the frequency dividers, i simply change the capacitors to change the range of the pll or gate frequency...
Another question is, why in the schematic posted the coils are not represented as in the original drawing where they were clearly opposing each other?
Best regards
