WFC VIC

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No I've never seen any of the circuits in the GMS. It's definitely not a 555, for one he shows in the schematic that there are 10 connections, a 555 only  has 8 pins. The reason for the logic gates and the capacitor are to convert the duty cycles of the incoming puts to a very short pulse duty cycle to be used as a trigger for the 74122 chip. Once I finish putting this circuit together, I will show u guys what I'm talking about.

(http://www.globalkast.com/images/tonywoodside/fig6_trigger.PNG)

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No I've never seen any of the circuits in the GMS. It's definitely not a 555, for one he shows in the schematic that there are 10 connections, a 555 only  has 8 pins. The reason for the logic gates and the capacitor are to convert the duty cycles of the incoming puts to a very short pulse duty cycle to be used as a trigger for the 74122 chip. Once I finish putting this circuit together, I will show u guys what I'm talking about.

@ Tony:
Thanks for being understanding...ive been trying to figure this control circuit out for a year or more...
heres a question to consider based on the diagram attached...

If Fig. (12 or 9xB) is the clock that times the whole circuit... that goes to point "G"
Point "G" is the Figure 2  "GAS PEDAL" mechanical PWM

Stans design used a variable duty cycle to provide more or less hydroxy gas based on throttle position

point "G" becomes a 10% - 90% duty cycle at a given clock frequency which is sent to TWO outputs ( M & M1 )

"M" goes on the top side of the VIC through fig 3 & 4 to create a variable voltage which is adjustable to provide a minimum idle speed at the low end and a maximum 12 volts at the passing speed / full throttle / 90% duty cycle setting

"M1" goes to the bottom side through figure 6 and on to PLL / resonant scanner / pulse pickup / and the result goes to the bottom or "Ground" / "negative" side of the VIC coil through Fig 5


Here is the question... if the clock frequency at the input of figure2 is fixed and the pulse width is variable at the same clock frequency... wont the trigger from the NORs on fig6 stay at a fixed frequency regardless of the throttle position

therefore wont the gating be fixed?

I believe the gating of the signal going into or stepping on the PLL frequency needed to follow the figure 2 Pulse Width to provide a Hydrogen output range from idle to full W.O.T. ( wide open throttle)

SO the way i see it is this, there are 3 parameters at work in the system:

1. variable positive voltage tied to gas pedal from 1, 2, or 3 volts to 12 ( based on idle requirement) to top of coil

2. resonant frequency based on pulse pickup being generated and sent to figure 5 via PLL ( not controlled by figure 2)

3. additional gas output control based on variable GATING that "steps on " the PLL signal sent to figure 5 that is determined by Figure 2 PWM or throttle position

do i have the flow chart figured out correctly?
( see attached)

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ok let me see if I can answer these questions for ya. Fig. 12 generates the gate frequency, lets say 500 Hz @ 50% duty cycle, which is then sent to fig. 2 via input "G". The duty cycle of this frequency will then be varied from 10% - 90% depending on the W.O.T. and rotation speed of the Distributor LED pickups. All these combined will determine the amount of voltage being applied to the Primary coil. This same frequency from fig. 12 will be sent to fig. 6 via input "B" or from fig. 2 via input "M1". This 500 Hz frequency's duty cycle is then manually set between 10% - 90% duty cycle independent of fig. 2. This variable gated pulse is then input into the PLL circuit via pin 5 through the two NOR gates and if you notice at the 2nd NOR gate u have the resonant frequency being NORed will the gate pulse. The PLL will output the the resonant frequency at pin 4 which is then routed back through pin 3 and into the 2nd NOR gate. The truth table for a NOR gate shows that you will get a HIGH only when both inputs are LOW. So the longer the gate pulse time is off, the more resonant pulses you will get into pin 5 via the NOR gate. This resonant frequency is steadily being match with the frequency from the feedback which is sent into the PLL via pin 14. Hope this helped answer some of your questions. I will try to draw up a logical output for the circuit and post it on here sometime this week.

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Eccelent general explanation, tony.
Yesterday I had some time to examin the circuit board pictures.
 
1/ What I`v noticed as Dynadon pointed out was that there is another 741 connected in parallel with the A25(741) of fig4. however still there is no extra connection for the input of the extra opamp!( extra J input if you like). pin 3 seems to be connected to a 47k  and then to Vdd.
 
2/ fig7 4017 dividers are not connected ok, but how and were pll pin 4 is connected to pin 5 I cannot locate. were is it?
 
HM
 

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Eccelent general explanation, tony.
Yesterday I had some time to examin the circuit board pictures.
 
1/ What I`v noticed as Dynadon pointed out was that there is another 741 connected in parallel with the A25(741) of fig4. however still there is no extra connection for the input of the extra opamp!( extra J input if you like). pin 3 seems to be connected to a 47k  and then to Vdd.
 
2/ fig7 4017 dividers are not connected ok, but how and were pll pin 4 is connected to pin 5 I cannot locate. were is it?
 
HM

here is a circuit to work with for the VIC CARD for multisim 11, many of the traces have been figured out but not 100% yet
please contribute and re-post !
thanks

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hydrogenmask,pin 3 of the PLL 4046 is the comparator in pin.That signal comes right from the negative side of the primary coil through a 22k resistor.Thats the small blue jumper wire on the front of the VIC board.It also goes to the ANL/FREQ switch on the front panel,and then that signal goes to the BNC test connector for scope reading.
 
Pin 4 goes into G on the cell driver circuit,and pin 5 is the inhibit input from the 4001 from the Gate Pulse circuit A.
 
Pin 4 and 5 are not connected together anywhere.If someone shows it that way,their wrong.
The 4017's are not used.
 
Don   

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this is what i came up with as the op amp side of the circuit

(http://i82.photobucket.com/albums/j243/outlawstc/water%20fuel%20tech/opampsschematic.jpg)

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hydrogenmask,pin 3 of the PLL 4046 is the comparator in pin.That signal comes right from the negative side of the primary coil through a 22k resistor.Thats the small blue jumper wire on the front of the VIC board.It also goes to the ANL/FREQ switch on the front panel,and then that signal goes to the BNC test connector for scope reading.
 
Pin 4 goes into G on the cell driver circuit,and pin 5 is the inhibit input from the 4001 from the Gate Pulse circuit A.
 
Pin 4 and 5 are not connected together anywhere.If someone shows it that way,their wrong.
The 4017's are not used.
 
Don

sorry Don, I made a mistake in my post I meant connection between pin3 and pin4 not pin5.
should they be connected to each other?

to pin 3 I see the following:
I see a blue wire (1st to the left going to the first 10k resistor of the ''cell driver circuit'')
Then I also can see another blue wire that may be also connected but not shown clear (right one connected to the 22k and small cap) shown in pic below.
 
Can you confirm Don?

HM