Author Topic: My pll circuit  (Read 24546 times)

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Re: My pll circuit
« Reply #24 on: September 24, 2012, 20:09:29 pm »
so i guess i was correct... try to do the modification i explained exchanging the 11 by the 12 and now it should be ok!

I'm happy that i was not wasting my time somehow looking into that...

So what was happening until now when it was showing I was getting resonance?

TS

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Re: My pll circuit
« Reply #25 on: September 24, 2012, 20:23:13 pm »
probably it was showing properly the lock in but not sending the right pulses... the way its wired it sends 1 pulse for each 10 pulses but is not a 1/10 of the frequency only its 1/10th of the duty cycle also...

basicaly if your frequency without dividing is 10khz the cycle time is 0.0001s so duty cycle is 50us.... i'm saying that when dividing this way you still send the same pulse but you wait ten pulses to send it again...probably it doubles the pulse width.. maybe not... if divide by 100 same pulse but one each 100 pulses..

I could be wrong...

I don't know what are the wave forms getting out of yours boards since i don't have a copy of them here... I'm pointing out that is different from stans diagrams and the original card configuration... from mine and from theory too... haha

i could try to make this wrong circuit to check... later i do it..

as i'm saying... to verify if its locking in...
you got to look at the pin 14 and pin 3 at the oscilloscope and they must be lock in... at my circuit the led turns off as it lose lock... way to see the lock in is to select the trigger only of one of the channels of the oscilloscope, such that if there is lock condition both waves still locked.. if you change the frequency going into pin 14 it should be able to follow it locked... when it looses lock the channel with no trigger will disappear or start to walk on the line in respect to the other... and led will turn off...

simple as that

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Re: My pll circuit
« Reply #26 on: September 24, 2012, 20:50:29 pm »
probably it was showing properly the lock in but not sending the right pulses... the way its wired it sends 1 pulse for each 10 pulses but is not a 1/10 of the frequency only its 1/10th of the duty cycle also...

basicaly if your frequency without dividing is 10khz the cycle time is 0.0001s so duty cycle is 50us.... i'm saying that when dividing this way you still send the same pulse but you wait ten pulses to send it again...probably it doubles the pulse width.. maybe not... if divide by 100 same pulse but one each 100 pulses..

I could be wrong...

I don't know what are the wave forms getting out of yours boards since i don't have a copy of them here... I'm pointing out that is different from stans diagrams and the original card configuration... from mine and from theory too... haha

i could try to make this wrong circuit to check... later i do it..

as i'm saying... to verify if its locking in...
you got to look at the pin 14 and pin 3 at the oscilloscope and they must be lock in... at my circuit the led turns off as it lose lock... way to see the lock in is to select the trigger only of one of the channels of the oscilloscope, such that if there is lock condition both waves still locked.. if you change the frequency going into pin 14 it should be able to follow it locked... when it looses lock the channel with no trigger will disappear or start to walk on the line in respect to the other... and led will turn off...

simple as that

As I'm looking at the datasheet, it seems to me that it doesn't really change the timing as much as pin 12 is used for the trigger pin when you have 4017's in series.  Pin 12 from what I read is still the same timing as the other pins such as 11, but basically is the 10 count where 11 is the 9 count.

I have been somewhat concerned about the duty cycle however.  It didn't seem to tune right.  Additionally, I have another PWM circuit by ZeroFossilFuel when seems to provide much better current draw at the same frequencies.

TS

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Re: My pll circuit
« Reply #27 on: September 24, 2012, 20:57:02 pm »
Yes thinking about it when you think it in series maybe theres no problem too... the problem this schematic is using the 11 as the output.. in the datasheet you see the wave form of the 11pin...  which is the 9 actually its the 10 output since it counts from zero... what i'm stressing is that you are not using the pll as desired this way.. since will only send a small pulse ... probably is why you are all getting so small amps...

at the first image of the 4017 circuits document on my last post... its clear what is happening... its wired just the same... at pin 11 it will light only every ten pulses for 1/10 of the time you see?...

I would guess that when you use your dividers (i mean at "lower frequencies") the amp draw does not increase much does it? probably not as it should...

I'm curious what Tony have to say about it....

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Re: My pll circuit
« Reply #28 on: September 24, 2012, 22:16:37 pm »
I find that the TIP120 overheats way too much sometimes.  For scaling up I think a higher rating transistor should be used. Opinions?

http://www.digikey.ca/product-detail/en/TIP35CG/TIP35CGOS-ND/920348

TS

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Re: My pll circuit
« Reply #29 on: September 25, 2012, 00:24:49 am »
so i guess i was correct... try to do the modification i explained exchanging the 11 by the 12 and now it should be ok!

I'm happy that i was not wasting my time somehow looking into that...

Dude, that was brilliant!!   Scan tracking is now working!  (Which was not before)

Not only is scan tracking working,it actually scanned, locked and is tracking a frequency outside the original scanning range!

Thanks a million.  I'll need to find a way to return the favour at some point.

TS

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Re: My pll circuit
« Reply #30 on: September 25, 2012, 03:26:59 am »
Happy to know it worked =) things still works as suppose to... 

Hope now you can make better tests my friend and friends...

Lets keep up with the work than...

Today i tested wiring up the output of the pin 3 to the input of the feed back circuit, if i input at one input it locks in and on the other it won't... anyway there's not specific resonant frequency so its only locking to the lowest frequency possible... it acquires lock at the top of the frequency range and than goes down within a characteristic time.. oh and strangely theres 180° between input and output although it shows lock... i guess its still trying to goes down in frequency... not sure... however is not important because is not a real world situation..

tomorrow is the day... real tests with the     vic transformer and cell ...

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Re: My pll circuit
« Reply #31 on: September 25, 2012, 04:24:40 am »
TS would you mind make some tests with your circuit for me?

just a few...

you can do all just taking the chip out and curling the pin so it don't get into the hole... just be careful to not breaking it..

disconnect the pin 14 of the pll

set it to manual scanning and measure the min, max voltages at pin 9...

disconnect pin 12 and measure the max and min frequencies changing the manual scanning max/min and the R1 pot set to max/min...
 i guess in your circuit the pot is connected to pin 11... is it correct?
re-conect the pin 12 and measure again max and min frequencies with same last procedure

If that is so probably is wiser than the way i tried... i will give it a try.. anyway in my config i have set the center frequency and give to it an off set this way i keep the bandwidth under control... don't know if is the best way... i will think about during my dreams...