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Projects by members => Projects by members => Sebosfato => Topic started by: sebosfato on September 15, 2012, 22:57:43 pm

Title: My pll circuit
Post by: Login to see usernames on September 15, 2012, 22:57:43 pm
I completed the pll circuit... I just decided to not construct the scanning because there was no space left at my solder less breadboard... with the oscilloscope i could determine the functioning of the lock in indicator and feed back circuit...

The lock in led will light if the phases between the signals coming from pin 1 and 2 from the cd4046 are within the range determined by the capacitor at the lock in circuit. this used the 74 002 nor gates 5volts chips... high speed !

The pulse indicator circuit need a high speed op-amp to be able to add as little phase delay as possible to the feedback signal. Here according to the analysis that tony made from the vic, he seem to have used the nte918

I wired the output of the pll to a not gate and connected to the pulse indicator to determine this... up to around 7 khz the ua741 op-amp still lock in...

I will get the better components to test it..



Title: Re: My pll circuit
Post by: Login to see usernames on September 17, 2012, 13:00:09 pm
I couldn't find the nte or ecg 918 opamp at my electronic parts supplier so i'm going to use instead the LM318 that has similar  slew rates high speed capabilities...

I guess this new circuit will lock in up to more several kilohertz since it wont add up much phase delay to the feed back signal.

Stan didn't wired up the output pin four of the pll straight to pin 3... why.. to add some delay to the line in such way to allow for the signal from the feed back be able to lock in at greater frequencies...  I would guess... this delay caused by the driver circuit, the stages of transistors adds maybe up to 100ns or more delay to the signal... so the feedback phase delay problem that arise with increasing frequency can be minimized... 

Now is clear why circuits i did in the past wasn't able to lock in at higher frequency i was using the lm741 opamps like... as i didn't had a good oscilloscope i could not see this differences clearly... nor i knew much about all this at the time i started playing with it.

With the pll stabilized the signal become really clean...

PLL's are used for generating highly stable frequency and is able to modulate it with low noise if properly setup.

hope you enjoy this info...

Title: The lock in led
Post by: Login to see usernames on September 18, 2012, 18:52:46 pm
I read more about pll's to understand better how this lock in indicator circuit works...

I found that the led will light brightly when the signal coming from the pll pin 1 is dc, this means there is no phase difference between the signal going into pins 3 and 14...

The diode and resistor combination allow the capacitor at the lock in circuit to get charged in a small time if out of lock happens and take more time to discharge... so only when its discharged there is a lock indication...

Title: The feed back signal
Post by: Login to see usernames on September 18, 2012, 19:31:08 pm
If the feedback signal comes from a coil in the vic transformer it will tend to tune in to the self resonance of the vic coils inductance capacitance... not a resonance of a resonant circuit.. i guess thats why stan uses so small signal transistors...

That being the case the inductor becomes a high impedance to the flow of amps as more amps develops more volts at resonance... Its should behave like a line transmission, with distribute capacitance and inductances... like many parallel tanks in series.

if this is the case the resonance across each turn will add up volts together... as the coils are not perfectly arranged theres not only one resonance frequency there is one that is central dominant because the inductors compensate as they are a series coupled inductors...

Once i got this effect unfortunately at that time the transformer wasn't connected properly to the cell and it burned into a blue fire... i was using steel coil that was covered with a black insulation like.

The pll was tuned manually to the frequency, without any feedback... probably the material of the wire helped because widened the bandwidth...

it was october 2008 if i remember well...

I thought this snubber circuit to be able to stop burning the switches... i have no money left for them ha..

notice that as the capacitor try to charge with greater voltage than source voltage the diodes allow the capacitor to be charged to a safe voltage and be discharged thru the coil during the switch on time, making use of some of this wasted energy... another switch could be added to allow the pulse to collapse all into the capacitor than direct it across the coil... a diode in series with the dc source will prevent the recharging effect protecting the source...
Title: Re: My pll circuit
Post by: Login to see usernames on September 19, 2012, 02:57:38 am
very efficient design!



Title: The gate signal
Post by: Login to see usernames on September 19, 2012, 10:38:00 am
Although i designed my own gate circuit to gate the pll, i was curious to understand better why meyer did things the way he did, so i started to take a look into how he generated the gate signal and why principally.

He uses a 555 timer and a set of frequency dividers 1/10, this means the range of precision of frequency is higher at lower frequencies.

He than uses a simple circuit that allows him to create a small pulse proportional to this clock signal, this short pulse goes to the 74ls122 chip which than generates the gate duty cycle adjustment from this small pulse length to 100%

the circuit that creates the short pulses is this:

ps the bigger the capacitor the bigger is the time to turn on, and the wider is the shortest pulse.. remember the pulse is proportional to frequency, given its a kind of RC network...




A stable gate frequency could be useful if we instead of using the pll as a frequency generator we use it as a pulse modulator...

I mean it can also work as a frequency multiplier i found at a book, so it can generates harmonics of a fundamental frequencies, instead of usual use as sub harmonic generator...

Title: The feed back signal
Post by: Login to see usernames on September 19, 2012, 13:03:54 pm
 I'm looking into my pll frequency follower... ;D

 Its now able to follow another frequency source but a bit lossy i'm improving it...

I found that maybe the pulse indicator circuit was wrong designed on stans schematics because it wasn't turning off the lights if theres no pulse detected... I fixed it inverting the inputs... I mean where the 5v signal goes to.

Thats why i have my doubts if is good or no to take a board ready from someone for example... since they are based on copy not design... at least it seems to me...

If you connect a 5 v to the + side of the opamp and the signal is not coming to the neg. input , the led still light because the output of the opamp will be positive...  of course!

referring to the diagram in attachment...

in the patent indeed both inputs are brought to same potential vdd... 

I'm also thinking about use active filtering this way better and faster lock in can be assured... all it takes is another opamp wired as voltage follower connected from pin 13 to 9... this enhances the ability of the phase comparator to charge or discharge the filter capacitor... 

I'm using only a manual adjustment of the frequency, so i added a 200k pot between the voltage divider signal setting the frequency and pin 9 this way if the system is close to resonance the impedance is high enough for the pll to take place regulating the filters voltage.

If no signal is detected the frequency goes to a minimum according to 4046 datasheets if using the phase comparator 2...

Title: Re: My pll circuit
Post by: Login to see usernames on September 19, 2012, 14:39:17 pm
Yet about this diagram the signal going thru a 22kohm resistor at the primary going straight to the pin 3 of the pll might also be wrong, except a zener diode is added, in the place or in parallel with that 10pf capacitor to prevent over voltages... otherwise if you put power into the circuit the  pll chip  could burns...  I guess the best option is to take this signal from the base of the last transistor...




Title: Re: My pll circuit
Post by: Login to see usernames on September 20, 2012, 22:03:32 pm
today i made some comparisons  between the different pll chips i have here...

I have the HEF4046, CD4046CN, CD4046BE, HCT7046, MC14046


The hct7046 works at 5 volts and puts out incredibly high frequencies!!! up to and beyond 10 megahetz if want perfect square wave...

The MC14046 has a strange behavior with meyer circuit, when the pin 5 is disabled, it oscillates at 13,6MHz a kind of noize it even keep the led on... I tried to add a 220pf capacitor to pin 3 and ground and this frequency became 9MHz


The cd4046be gives the lowest frequencies... followed by hef and cd4046cn...





Title: R2 frequency of set...
Post by: Login to see usernames on September 21, 2012, 12:31:02 pm
Reading the hct7046 datasheet i discovered something i didn't understood fully

The capture range of the pll is within the frequency determined by R1 and C1 being R2 infinite...

If R2 is not infinite this lock range center max and minimum frequency  will fluctuate up varying the R2.

This is highly important because this is why he used a pot for the R2 and a pot for manual frequency adjustment

The R2 sets the range max min frequencies at which the pll will try to tune in... the smaller the r2 the higher the frequency and smaller the bandwidth i would guess..

Title: Re: My pll circuit
Post by: Login to see usernames on September 21, 2012, 19:15:06 pm
That last info is the base of all working of the pll

Basically i found out that:

In my case R1 = 100k C1=10nf  R2= 10k-220k  pot... different pll chips will have different bandwidth and off sets, and linearities with same components...

R1 C1 sets the frequency lock range... for example being R2 infinite, this makes a frequency that goes from 0 up to 2khz this means a 2khz bandwidth--- being the center 1khz so it can lock to whatever frequency within this bandwidth.


The frequency off set maintain this lock range while allowing you to look into a greater range of frequencies while preserving this same bandwidth-..

so for example

Now if you add R2 say 100kohm this center frequency of 1khz jumps to to 2khz so it can lock from 1khz up to 3khz, you can check the bandwidth varying pins 9 voltage (vco) from 0 to vcc

Now lets say you reduce this R2 to 10kohm, now the center frequency is 12khz for example so you can regulate from 11khz up to 13khz

This R2 must be tuned to allow the lock range to be in the range of the frequency being received by the pll from the feedback...

By the way if you divide by 10 the frequency the bandwidth will be 10x narrower so as will ALSO be the off set, so the bandwidth will stays within a certain % range of the off set frequency...

If i recall well meyer mentioned 20%...

I took some LONG time to grasp this idea only reading the datasheets..

I guess is clear enough now for all to understand,

 i hope you enjoy...


Title: My pll circuit Works!!!!!!!
Post by: Login to see usernames on September 22, 2012, 20:25:29 pm
well now my pll is fully working, including the lock in indicator, pulse indicator, feedback...
i would like to show to you but got no camera here..
The manual frequency tuning is not even required for it to achieve lock in condition (i simply disconnected it from pin 9... and its able to follow a frequency within the bandwidth programed!!!!

The filter is also not critical, i used R3 33k resistor from pin 13 to 9 and a 1nf capacitor connected to ground...

i used a 10nf for the lock in circuit with a 100k resistor and 1n4148 diode and it lights only if there is lock in or close to... at all other frequencies it will stay off...

I don't know why i waited so long to get a real oscilloscope now i'm willing to see how far can i go now!
Title: Re: My pll circuit
Post by: Login to see usernames on September 22, 2012, 20:31:20 pm
So far i discovered that the bandwidth % is not fixed and get smaller at higher frequencies, to get around, the circuit bandwidth can be tuned changing R1 or C1

increasing R1 or C1 decreases the bandwidth as it reduce the center frequency...

The R1/C1 ratio also plays

bandwidth=Fmax-Fmin where Fmax=2F0

I'm thinking about here... a way to achieve a more linear behavior would be to make R1 smaller C1 bigger. ...  thats because i think the problem of linearity start to arise when R2 is too much smaller than R1...
Title: Great Great news!
Post by: Login to see usernames on September 23, 2012, 16:54:16 pm
It ended up that i was right about the R2/R1 relation, as it become lower than 1 the linearity become poor.

I changed the R1 to 10k, the C1 now is 1nf and simply disconnected not only the manual tuning but also R2
at the filter now there is a r4 resistor 10k between the a 10nf capacitor and ground... this improved a lot stability of the lock

The circuit is now able to automatically tune into whatever frequency from 1khz up to 100khz... or more or less i didn't tested all the range hahah

its amazing


It will never lose the lock in condition.. the led stays light!!! the lock in led still 10nf...

0 ZERO phase difference between input at pin 14 and output... within all this tested range... instant lock...

oh and it also lock in when dividing the frequency with the 4017 chips, no worries about that too...

now is time to play!!!!!!!!

Regards
Title: Re: Great Great news!
Post by: Login to see usernames on September 23, 2012, 17:51:20 pm
It ended up that i was right about the R2/R1 relation, as it become lower than 1 the linearity become poor.

I changed the R1 to 10k, the C1 now is 1nf and simply disconnected not only the manual tuning but also R2
at the filter now there is a r4 resistor 10k between the a 10nf capacitor and ground... this improved a lot stability of the lock

The circuit is now able to automatically tune into whatever frequency from 1khz up to 100khz... or more or less i didn't tested all the range hahah

its amazing


It will never lose the lock in condition.. the led stays light!!! the lock in led still 10nf...

0 ZERO phase difference between input at pin 14 and output... within all this tested range... instant lock...

oh and it also lock in when dividing the frequency with the 4017 chips, no worries about that too...

now is time to play!!!!!!!!

Regards

Congratulations! :) :) :)
Well done!

Steve
Title: Re: My pll circuit
Post by: Login to see usernames on September 23, 2012, 17:56:55 pm
I found that R2 might still useful to limit the range of frequencies.. and that at lower much lower frequency the filter capacitor must be increased or strange pulses will come out with strange duty cycles... The damping resistor R4 is there to help to avoid oscillation at the filter capacitor, as it tries to find the right vco voltage, this way the capacitor can be smaller so the lock in is faster...

 i tested up to 47uf at the filter... you can see it tuning at slowmotion with high capacitors walue when you change the frequency...

Title: Re: My pll circuit
Post by: Login to see usernames on September 23, 2012, 20:04:25 pm
Are you going to give us a schematic of your circuit?

 ;)

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 23, 2012, 20:06:24 pm
TS is the same schematic of the complete vic tony is selling, stans schematic... but i changed some values because with those values it was not working for me... i used the components i got here standard values for example 100k 10k 10nf 1nf 100nf 1k 1M the only different i got is 2,2k all other values i make with combinations therefrom...

ohh the only difference is the gate pulse generator which is a bit different since i use the 555 and a 741 to make it.. like all my olders schematics
things only changed in the sense that now i use 4001 instead of sn74hc02 because the lm318 wasn't working so good at 5 v

I use only one 1/10  cd4017... don't see why use more...

you need to work with the components you got there you got it...

Well this is the most affordable stable and simple pll frequency generator i ever achieved...

I'm using mainly 9 IC components... cd4046BE, HD4001, Lm318, cd4017, lm7812, lm7815, ir4427, NE555, LM741 AND, some small signal transistors 2N3904, diodes resistors and capacitors

i use the 15v only for the ir4427 chip.. because its better to drive mosfets..

the lm318 is a direct replacement of the ecg918 which i could't buy here...

The best configuration UNTIL NOW i found to be

R1=10k pin11-gnd
R2=10k+200k pot  pin 12-gnd
R3=100k pin 13-9
R4=10k damping resistor filter cap.->ground
R5=50k lock in resistor parallel with 1n4148 diode in the lock in circuit
C1=1nf - 11nf timing capacitor  pins6-7
C2=20nf filter capacitor pin 9-> damping resistor ->ground
C3=10nf lock in capacitor


With this components, i could achieve perfect lock in indication and lock in condition from 500hz up to 250khz...

i think could go higher lowering the timing capacitor... worth for tesla coils..

At lower frequencies it become non stable... so filter capacitor can be increased for that situations... i believe max 100nf is enough..
Title: Probably the vic cards you guys bought has hugely wrong connections
Post by: Login to see usernames on September 24, 2012, 13:42:55 pm
I was drawing a schematic of my current pll when i noticed that the schematic around for the vic production has huge problems...

Probably you got it completely wrong working...

They are connecting as the output of the frequency dividers 4017 instead of pin 12 which would be the 1/10 output, it wired at pin 11... look at the data sheet to see whats the difference...

incredibly at the vic images (pics) the 12 pin is used not the 11... check your circuits to see if i'm not right...

Basically your circuits are not 1/10 , it puts out 1 pulse for each 10 pulses coming in... completely wrong!!!!!!!!!!!!!!!!!!!!!!!!!!!

You are welcome...

Notice at the first attachment that this drawing was a copy of the vic and this is indeed correct...

However at the 2 and 3 attachment wherever you look its wrong wired!!!!

Last but not least...
the 4 attachment is my schematic... on progress... should be 100million times better...
no resonant scanning connected...
feedback circuit corrected too...
The gate generator goes from 0 to 100% duty cycle---

Strange enough all my schematics was correct and worked as thought using the pin12 of the 4017... since 2008

was this a confusion only by their side while making the drawings?
hope so
but how many are around?
anyone found this issue?
oh boy

If you bought those cards and they are wrong as i pointed you can simply disconnect from pin 11 and connect to pin 12... your lucky its close to one another...

please someone tell those guys using it and selling it, about this...

If any of you feel thank full by any reason...

i'm accepting help...
Title: Re: Probably the vic cards you guys bought has hugely wrong connections
Post by: Login to see usernames on September 24, 2012, 15:29:15 pm
I was drawing a schematic of my current pll when i noticed that the schematic around for the vic production has huge problems...

Probably you got it completely wrong working...

They are connecting as the output of the frequency dividers 4017 instead of pin 12 which would be the 1/10 output, it wired at pin 11... look at the data sheet to see whats the difference...

incredibly at the vic images (pics) the 12 pin is used not the 11... check your circuits to see if i'm not right...

Basically your circuits are not 1/10 , it puts out 1 pulse for each 10 pulses coming in... completely wrong!!!!!!!!!!!!!!!!!!!!!!!!!!!

You are welcome...

Notice at the first attachment that this drawing was a copy of the vic and this is indeed correct...

However at the 2 and 3 attachment wherever you look its wrong wired!!!!

Last but not least...
the 4 attachment is my schematic... on progress... should be 100million times better...
no resonant scanning connected...
feedback circuit corrected too...
The gate generator goes from 0 to 100% duty cycle---

Strange enough all my schematics was correct and worked as thought using the pin12 of the 4017... since 2008

was this a confusion only by their side while making the drawings?
hope so
but how many are around?
anyone found this issue?
oh boy

If you bought those cards and they are wrong as i pointed you can simply disconnect from pin 11 and connect to pin 12... your lucky its close to one another...

please someone tell those guys using it and selling it, about this...

If any of you feel thank full by any reason...

i'm accepting help...

Thanks Sebosfasto, I'll be checking mine.  I also want to get frequencies above the 10kHz current setup too.  Glad we have people who have got a good eye for circuits.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 24, 2012, 18:30:10 pm
How about it, could you imagined it?  8)

hope is easy enough to get around this problem.... you can cut the 11pin from the chip and put the 12 on the 11 hole...

or you can simply solder a small wire...

waiting to see if it were wrong or correct just for fun...

I'm now working to get this pll to do what i want it to do!!! hydrogen!
Title: Re: My pll circuit
Post by: Login to see usernames on September 24, 2012, 19:58:14 pm
I'm impressed that its being a while since this schematics are up there... i newer tried it because i was always working at my own designs... thats why only now i found this errors...

strange enough

Did you found it? 

I guess you will be able to lock in better now TS...  ;)
Title: Re: My pll circuit
Post by: Login to see usernames on September 24, 2012, 20:00:38 pm
Anyone noticed it?

My board is wired to pin 11.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 24, 2012, 20:05:16 pm
so i guess i was correct... try to do the modification i explained exchanging the 11 by the 12 and now it should be ok!

I'm happy that i was not wasting my time somehow looking into that...
Title: Re: My pll circuit
Post by: Login to see usernames on September 24, 2012, 20:09:29 pm
so i guess i was correct... try to do the modification i explained exchanging the 11 by the 12 and now it should be ok!

I'm happy that i was not wasting my time somehow looking into that...

So what was happening until now when it was showing I was getting resonance?

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 24, 2012, 20:23:13 pm
probably it was showing properly the lock in but not sending the right pulses... the way its wired it sends 1 pulse for each 10 pulses but is not a 1/10 of the frequency only its 1/10th of the duty cycle also...

basicaly if your frequency without dividing is 10khz the cycle time is 0.0001s so duty cycle is 50us.... i'm saying that when dividing this way you still send the same pulse but you wait ten pulses to send it again...probably it doubles the pulse width.. maybe not... if divide by 100 same pulse but one each 100 pulses..

I could be wrong...

I don't know what are the wave forms getting out of yours boards since i don't have a copy of them here... I'm pointing out that is different from stans diagrams and the original card configuration... from mine and from theory too... haha

i could try to make this wrong circuit to check... later i do it..

as i'm saying... to verify if its locking in...
you got to look at the pin 14 and pin 3 at the oscilloscope and they must be lock in... at my circuit the led turns off as it lose lock... way to see the lock in is to select the trigger only of one of the channels of the oscilloscope, such that if there is lock condition both waves still locked.. if you change the frequency going into pin 14 it should be able to follow it locked... when it looses lock the channel with no trigger will disappear or start to walk on the line in respect to the other... and led will turn off...

simple as that
Title: Re: My pll circuit
Post by: Login to see usernames on September 24, 2012, 20:50:29 pm
probably it was showing properly the lock in but not sending the right pulses... the way its wired it sends 1 pulse for each 10 pulses but is not a 1/10 of the frequency only its 1/10th of the duty cycle also...

basicaly if your frequency without dividing is 10khz the cycle time is 0.0001s so duty cycle is 50us.... i'm saying that when dividing this way you still send the same pulse but you wait ten pulses to send it again...probably it doubles the pulse width.. maybe not... if divide by 100 same pulse but one each 100 pulses..

I could be wrong...

I don't know what are the wave forms getting out of yours boards since i don't have a copy of them here... I'm pointing out that is different from stans diagrams and the original card configuration... from mine and from theory too... haha

i could try to make this wrong circuit to check... later i do it..

as i'm saying... to verify if its locking in...
you got to look at the pin 14 and pin 3 at the oscilloscope and they must be lock in... at my circuit the led turns off as it lose lock... way to see the lock in is to select the trigger only of one of the channels of the oscilloscope, such that if there is lock condition both waves still locked.. if you change the frequency going into pin 14 it should be able to follow it locked... when it looses lock the channel with no trigger will disappear or start to walk on the line in respect to the other... and led will turn off...

simple as that

As I'm looking at the datasheet, it seems to me that it doesn't really change the timing as much as pin 12 is used for the trigger pin when you have 4017's in series.  Pin 12 from what I read is still the same timing as the other pins such as 11, but basically is the 10 count where 11 is the 9 count.

I have been somewhat concerned about the duty cycle however.  It didn't seem to tune right.  Additionally, I have another PWM circuit by ZeroFossilFuel when seems to provide much better current draw at the same frequencies.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 24, 2012, 20:57:02 pm
Yes thinking about it when you think it in series maybe theres no problem too... the problem this schematic is using the 11 as the output.. in the datasheet you see the wave form of the 11pin...  which is the 9 actually its the 10 output since it counts from zero... what i'm stressing is that you are not using the pll as desired this way.. since will only send a small pulse ... probably is why you are all getting so small amps...

at the first image of the 4017 circuits document on my last post... its clear what is happening... its wired just the same... at pin 11 it will light only every ten pulses for 1/10 of the time you see?...

I would guess that when you use your dividers (i mean at "lower frequencies") the amp draw does not increase much does it? probably not as it should...

I'm curious what Tony have to say about it....
Title: Re: My pll circuit
Post by: Login to see usernames on September 24, 2012, 22:16:37 pm
I find that the TIP120 overheats way too much sometimes.  For scaling up I think a higher rating transistor should be used. Opinions?

http://www.digikey.ca/product-detail/en/TIP35CG/TIP35CGOS-ND/920348

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 25, 2012, 00:24:49 am
so i guess i was correct... try to do the modification i explained exchanging the 11 by the 12 and now it should be ok!

I'm happy that i was not wasting my time somehow looking into that...

Dude, that was brilliant!!   Scan tracking is now working!  (Which was not before)

Not only is scan tracking working,it actually scanned, locked and is tracking a frequency outside the original scanning range!

Thanks a million.  I'll need to find a way to return the favour at some point.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 25, 2012, 03:26:59 am
Happy to know it worked =) things still works as suppose to... 

Hope now you can make better tests my friend and friends...

Lets keep up with the work than...

Today i tested wiring up the output of the pin 3 to the input of the feed back circuit, if i input at one input it locks in and on the other it won't... anyway there's not specific resonant frequency so its only locking to the lowest frequency possible... it acquires lock at the top of the frequency range and than goes down within a characteristic time.. oh and strangely theres 180° between input and output although it shows lock... i guess its still trying to goes down in frequency... not sure... however is not important because is not a real world situation..

tomorrow is the day... real tests with the     vic transformer and cell ...
Title: Re: My pll circuit
Post by: Login to see usernames on September 25, 2012, 04:24:40 am
TS would you mind make some tests with your circuit for me?

just a few...

you can do all just taking the chip out and curling the pin so it don't get into the hole... just be careful to not breaking it..

disconnect the pin 14 of the pll

set it to manual scanning and measure the min, max voltages at pin 9...

disconnect pin 12 and measure the max and min frequencies changing the manual scanning max/min and the R1 pot set to max/min...
 i guess in your circuit the pot is connected to pin 11... is it correct?
re-conect the pin 12 and measure again max and min frequencies with same last procedure

If that is so probably is wiser than the way i tried... i will give it a try.. anyway in my config i have set the center frequency and give to it an off set this way i keep the bandwidth under control... don't know if is the best way... i will think about during my dreams...


Title: Re: My pll circuit
Post by: Login to see usernames on September 25, 2012, 06:25:48 am
There is something I must very strongly emphasize.  The coils must be connected EXACTLY in the right way or none of this will work.  I am not talking just about the chokes either. The primary, secondary and chokes must ALL be connected with correct polarity according to their poles for the resonance to work properly.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 25, 2012, 07:49:41 am
I guess you mean choking the secondary voltage... and having right polarities relationship between primary secondary diode chokes and feedback coils right ..  ;D

I'm getting back to this hell soon.

My mind is blowing i simply continue non stop thinking about it all day night and dream... no rest no peace... being quite a long time
Title: Re: My pll circuit
Post by: Login to see usernames on September 25, 2012, 17:01:17 pm
I guess you mean choking the secondary voltage... and having right polarities relationship between primary secondary diode chokes and feedback coils right ..  ;D

I'm getting back to this hell soon.

My mind is blowing i simply continue non stop thinking about it all day night and dream... no rest no peace... being quite a long time

Which may seem rather odd, but I don't just mean relational to the other coils.  I have found at times that if I completely reverse all the connections it will work better even though logically it should behave exactly the same in theory.  There is definitely an "art" to this as Meyer's stated.

TS
Title: New schematic
Post by: Login to see usernames on September 25, 2012, 22:32:30 pm
This includes the correct coils polarities according to my theory...
Title: more updates newer schematic
Post by: Login to see usernames on September 26, 2012, 00:45:22 am
With this schematic if the output is connected to the input it will lock within all range from 1.5-250khz
the 220pf i added to the lock in circuit helps the led to indicate lock up to 500kz tested---


The alternative design is mostly according to stan schematic as possible.. it use opposite polarity for the feedback coil...
the not gate implemented will allow the led to light only when there are pulses going in, otherwise a PNP transistor could be used (without the not gate)... its an inverting amplifier in this case...

Title: Re: more updates newer schematic
Post by: Login to see usernames on September 26, 2012, 17:34:03 pm
With this schematic if the output is connected to the input it will lock within all range from 1.5-250khz
the 220pf i added to the lock in circuit helps the led to indicate lock up to 500kz tested---


The alternative design is mostly according to stan schematic as possible.. it use opposite polarity for the feedback coil...
the not gate implemented will allow the led to light only when there are pulses going in, otherwise a PNP transistor could be used (without the not gate)... its an inverting amplifier in this case...

Should be RESONANT with one N.  :)

Thanks for the updates.  I'll try some soon.  I'm hoping some of these modifications can be easily done on Tony's circuit board.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 26, 2012, 17:47:28 pm
I think is possible yes...

I tried to run the transformer and the result was unpredictable... the frequency become a function of the voltage applied.. if gated a kind of sweep is generated... i guess because of the filter components...

it locks at specific frequencies and something strange is happening theres a point where the frequency in the feed back doubles... now i need some time for the digestion...

oh and the multimeter connected to only circuit ground bips loud like if 1000v were applied between the leads... with as little as 10v applied...

the feedback coil i used same wire of the chokes... just some few turns maybe 10 or 20... wiorks perfectly... perfect square wave sometimes....

the voltage applied increases the frequency up to the maximum... at 12v or so it already reached 270khz... in my case

i'm connecting to the cell now...
Title: Re: My pll circuit
Post by: Login to see usernames on September 26, 2012, 17:48:40 pm
now i'm interested to know why he Stan... was also modulating the voltage...

This simple oscilloscope helped me a lot understand the things better...

Now it opened a whole new tests possibility for me... i will be aways trying to lock in to resonance...  8)
Title: Re: My pll circuit
Post by: Login to see usernames on September 26, 2012, 20:45:40 pm
For the life of me, I cannot figure out how I got it to scan and lock the first time I fixed pin 12.  It just worked when I turned it on the first time.  Since then, I have made 3 more coils, only one that worked equally well as the first and now I can't get either to lock and follow!

!!!!!!!!!!!!!!!!!!!!!!!!!!

I'll probably try, as you suggested, a simple pll on my solderless breadboard and see what it does.  I'm also wondering if something else on my TW VIC circuit is burned out somewhere in the PLL circuit (I previously burned out some IC's when I shorted the feedback wire to the WFC power wire).  I'm not sure that the gate pulse and/or duty cycle works correctly either.

So frustrating.  It seemed like I was almost there.

On a side note, on my original 5 strand bifilar, I wound a new primary around it to step up the original 5 strands.  With the extra 2 strands I now had, I hooked them up in series with the strands I used as chokes.  It seems to make a noticeable improvement in production.  It also seems to corelate to Meyer's Patent on page 10-12 in hooking up chokes in series.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 26, 2012, 21:19:07 pm
I got a high frequency burn on my hand hahah the spark jumped to my hand.-...

I think you could have burned some components..or coil... at this board the pin 3 is connected to the primary... with no zener protection i guess...
Find out how to test your components... and circuits...

I'm thinking about the sensibility of the feedback coil...

I think that if we pulse to hard the pulse indicator will pick this pulse not the resonance one... strangely when gating almost to 1 pulse i can see a kind of signal of different frequency following...

I guess mic transformer is already burned again... we smoked here...

many different strange noises when gating...

Tony answered to me and the correct pin was indeed the 12 pin, he simply made a mistake while making the boards...

Title: Re: My pll circuit
Post by: Login to see usernames on September 26, 2012, 21:33:59 pm
I'm thinking about the sensibility of the feedback coil...

I think that if we pulse to hard the pulse indicator will pick this pulse not the resonance one... strangely when gating almost to 1 pulse i can see a kind of signal of different frequency following...

Agreed.  I have noticed a feedback that is not resonance.  That's why I made a video about it.  :)

I have found true resonance come on, there will be little to no faint flickering.  It should be a hard on for the indicator LED.

What I noticed that I'm still trying to wrap my head around is that even though my circuit was scanning  from 1kHz to 4kHz, it locked at 0.5kHz.  And when it moved out of range and rescanned at the original 1kHz to 4kHz, it still relocked in at 0.5kHz.  There must have been enough time between pulses for the circuit to pick up that frequency.  A shorter duty cycle maybe.

Still a lot to learn in how this stuff operates.  :)

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 27, 2012, 04:46:05 am
I guess mic transformer is already burned again... we smoked here...

Is your primary the inside or outside coil?  If it is the inside coil that would be why you are burning it up.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 27, 2012, 04:56:23 am
In my case there is no inside coil... 5 coil vic... what would be the problem having it inside?

sebs
Title: Re: My pll circuit
Post by: Login to see usernames on September 27, 2012, 10:57:38 am
Anyone noticed it?

My board is wired to pin 11.

TS
Hey guys, lots happing here in this thread!
I'll checked my PCB and also pin 11 was wired instead of pin 12. Since this is a version 1 PCB.  8)

Regards
Title: Re: My pll circuit
Post by: Login to see usernames on September 27, 2012, 11:44:28 am
Hope you enjoy...

if you know about others using this board version would be nice to alert them too....

Regards

Title: Re: My pll circuit
Post by: Login to see usernames on September 27, 2012, 15:06:17 pm
In my case there is no inside coil... 5 coil vic... what would be the problem having it inside?

sebs

Any real VIC has at least 5 coils.  Just depends on how you wind them... :)

My experience with putting a primary coil on the inside is:

1.  It eats lots of amps

My experience with putting a primary coil on the outside is:

1.  It doesn't eat up lots of amps

My understanding is that the magnetic field generated by a coil is greater on the inside of said coil.   That being the case, you'd get better transference from the magnetic field when generating the magnetic field from the outside coil.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 27, 2012, 16:49:26 pm
The pulse indicator circuit should be arranged to not show pulses out of the resonance range... thats why the 5v is there and there is a resonant scanning circuit or manual tuning...

If the signal get resonance the output of the feedback coil is greater than 5v and so the pulses start to correctly feedback...

I found this in simulation...

So stan circuit is more correct, but like i said a pnp transistor should be used for the led to indicate correctly...

It act like a schimitt trigger somehow

If the led is off your are not close to resonance...

so the turns number are critical to set the sensibility.... and another thing is that is must do have a real resonance gain there otherwise no happy...
Title: Re: My pll circuit
Post by: Login to see usernames on September 27, 2012, 18:16:14 pm
The pulse indicator circuit should be arranged to not show pulses out of the resonance range... thats why the 5v is there and there is a resonant scanning circuit or manual tuning...

If the signal get resonance the output of the feedback coil is greater than 5v and so the pulses start to correctly feedback...

I found this in simulation...

So stan circuit is more correct, but like i said a pnp transistor should be used for the led to indicate correctly...

It act like a schimitt trigger somehow

If the led is off your are not close to resonance...

so the turns number are critical to set the sensibility.... and another thing is that is must do have a real resonance gain there otherwise no happy...

In other words, if your turns on your primary are 100 and your input voltage is 10V, then your pickup coil should be 50 turns or less?

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 27, 2012, 18:22:51 pm
probably something like that or less...

at least this makes sense... you can discriminate the frequencies by its signal level... otherwise it will try to tune to whatever signal it receives...

Stan called Resonance feedback, pulse indicator, meaning that it indicates where there is resonance...

the lock in led should light than only when lock to resonance...

 
Title: Re: My pll circuit
Post by: Login to see usernames on September 27, 2012, 18:29:10 pm
probably something like that or less...

at least this makes sense... you can discriminate the frequencies by its signal level... otherwise it will try to tune to whatever signal it receives...

Stan called Resonance feedback, pulse indicator, meaning that it indicates where there is resonance...

the lock in led should light than only when lock to resonance...

I always had a feeling it should be that way, until Tony's diagram said it should be the same.  Not to mention that in all of Meyers diagrams that the feedback coil is always demonstrated as being smaller.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 27, 2012, 18:40:50 pm
TS this is my analysis, and could also be wrong...

For me this explain why he used this 5v there and this inverting amplifier... otherwise like i pointed before he could have used non inverting amplifier but the impedance of the input is almost infinite so any signal is detected...

notice i connected the 5v to the positive input, so the output will only become low when the voltage at the inverting input is higher than the positive input...

I believe he set up the primary and the feedback coil and pulse it up to the point no signal is show than add the chokes and make it resonate to try detecting the frequency...

Title: Re: My pll circuit
Post by: Login to see usernames on September 28, 2012, 10:15:52 am
I just made a simulation... and seems like the pulse indicator circuit at the patent works kind of perfectly... respecting the fact voltage going in must be smaller than a certain threshold for pulses to not be detected all the time. if you add a capacitor than it captures the signal because the signal at resonance is stronger than with no resonance...

Stan talks about the signal being able to lock into molecular resonance... yes i read it again...
Title: Re: My pll circuit
Post by: Login to see usernames on September 28, 2012, 15:33:22 pm
I just made a simulation... and seems like the pulse indicator circuit at the patent works kind of perfectly... respecting the fact voltage going in must be smaller than a certain threshold for pulses to not be detected all the time. if you add a capacitor than it captures the signal because the signal at resonance is stronger than with no resonance...

Stan talks about the signal being able to lock into molecular resonance... yes i read it again...

Add capacitor where?

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 28, 2012, 16:18:04 pm
where you want,, whatever capacitor will form a resonant tank.... in series or parallel... 

I guess with the vic the chokes become the capacitance like---

Title: Re: My pll circuit
Post by: Login to see usernames on September 28, 2012, 17:41:19 pm
where you want,, whatever capacitor will form a resonant tank.... in series or parallel... 

I guess with the vic the chokes become the capacitance like---

Sorry, not quite following.  Putting just any capacitor in line with any coil will create resonance signals based on the induction and capacitance of the coil and capacitor's values.  It won't necessarily match the resonance of the VIC.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 28, 2012, 22:44:58 pm
I talking about working on the pulse indicator circuit to get it working... what you do later is another thing...

if you have only primary and feedback coil no reonance should result ...than adding a capacitor wherever you want will make of it a tuned circuit won't... 

sebosfato
Title: Re: My pll circuit
Post by: Login to see usernames on September 30, 2012, 21:16:00 pm
probably something like that or less...

at least this makes sense... you can discriminate the frequencies by its signal level... otherwise it will try to tune to whatever signal it receives...

Stan called Resonance feedback, pulse indicator, meaning that it indicates where there is resonance...

the lock in led should light than only when lock to resonance...

I always had a feeling it should be that way, until Tony's diagram said it should be the same.  Not to mention that in all of Meyers diagrams that the feedback coil is always demonstrated as being smaller.

TS

I've put a 5k resistor in line with the feedback coil that is the same length as the primary.  It locks resonance much better now.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on September 30, 2012, 22:38:08 pm
My experience so far is the larger the ratio of turns on the secondary, the lower the resonant frequency.  At 20:1 my resonant frequency drops to about 11Hz.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on October 01, 2012, 12:06:56 pm
Wow great info... could you explain a little further?
Title: Re: My pll circuit
Post by: Login to see usernames on October 01, 2012, 12:42:09 pm
Wow great info... could you explain a little further?

I'm working on some numbers.  I'll expand further when I can.   I was a little puzzled when my first step up locked in at 500Hz and expected the 20:1 to lock in with a higher frequency.  Even though it is still scanning with a frequency in the kHz range, the lock in frequency when probing the cell was still only 11Hz.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on October 01, 2012, 17:21:06 pm
Wow great info... could you explain a little further?

I'm working on some numbers.  I'll expand further when I can.   I was a little puzzled when my first step up locked in at 500Hz and expected the 20:1 to lock in with a higher frequency.  Even though it is still scanning with a frequency in the kHz range, the lock in frequency when probing the cell was still only 11Hz.

TS

In a way, it actually makes sense.  Since it it will take longer to charge and discharge a larger secondary than a smaller one.   

Actually, I was in error.  I was forgetting the fact the LC is tuned to resonance based on capacitor and inductor values.  Obviously, by the size of my cell, the higher number of turns I have done on my secondary necessitate a lower resonant frequency.  If I want a higher frequency, I need to lower the number of turns appropriately to match the capacitance of my cell.

That means I need a smaller secondary and even smaller primary if I want to step up the voltage. 

TS
Title: Re: My pll circuit
Post by: Login to see usernames on October 02, 2012, 04:43:59 am
Well done, hope you keep coming with more news.. i constructed today a new pll circuit, i added two more 1/10 to achieve lower freqs... i need to buy a new soldering iron i destructed mine while trying to change the point. i found it could be a good resistive choke if needed... just an idea...
Title: Re: My pll circuit
Post by: Login to see usernames on October 02, 2012, 12:56:14 pm
Well done, hope you keep coming with more news.. i constructed today a new pll circuit, i added two more 1/10 to achieve lower freqs... i need to buy a new soldering iron i destructed mine while trying to change the point. i found it could be a good resistive choke if needed... just an idea...

Stan's circuit seems to lock into any frequency as is.  I've seen it lock (briefly) even at 5Hz.

I'm starting to come to 2 theories. 

1.  This particular circuit that we are focusing on was designed to work primarily with Stan's water injectors
2.  The best production we will get will come from cells that have very small capacitance

I have 2 cells that I am focusing my attention on.  One is about 3/4" external diameter.  The other cell  is more like 1/8" external diameter.  Visually, on the same circuit using the same coil ( not at the same time), the smaller one always appears to have a higher production.

I see quite often attempts to make bigger coils and bigger cells.  I'm suspecting that this is counter productive, not to mention very expensive.  Creating a smaller coil and smaller cell for experimenting should be more than enough to provide a proof of concept as well as a working prototype that can be scaled up once a working system is discovered.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on October 02, 2012, 15:37:32 pm
TS, i hope you are wrong, in the sense that, like i was pointing, probably your feedback circuit is not rejecting non resonant signals...i mean its locking into the frequency itself sending to the vic... it will behave like if no signal was applied to the pin 14 and goes toward the lowest frequency of the vco...

as i also pointed before you might be varying the pot resistor r1 (pin 11) instead of r2 (pin 12)... r1 mess around with the center frequency broadening and narrowing the bandwidth, while r2 would only changes the off set letting you chose an R1 for a more or less fix and limited bandwidth... this is handy while trying to reject signals...


 i just made a mod in the feed back circuit...

the diagram by tony was correct in the end except by the position of the capacitor... it should be between the 5 v and the non inverting input of the opamp, of course having that 10k resistor therebetween...  lowering the 100k resistor and or raising the vdd applied increase the signal rejection.. your 5k resistor helped here, but probably is not enough specially if in your circuit that capacitor is at wrong position... because this would turn off the rejection of the opamp and would become only an amplifier, another drawback is the led indicating while no pulse present since the non inverting will be at higher potential than the inverting input...

I made a simulation and it works it is able to reject non resonant signals... of course the signal should be in the tens to hundreds of milivolts range


It hapens that when you apply a lower frequency than that of resonance the current applied oscillates, this oscillation has a stronger magnitude than the applied voltage when close to resonance so the limit is reached and the feedback circuit pick up the signal...


regards
Title: Re: My pll circuit
Post by: Login to see usernames on October 02, 2012, 16:21:13 pm
TS, i hope you are wrong, in the sense that, like i was pointing, probably your feedback circuit is not rejecting non resonant signals...i mean its locking into the frequency itself sending to the vic... it will behave like if no signal was applied to the pin 14 and goes toward the lowest frequency of the vco...

The circuit is locking into very specific frequency zones.  If it was doing as you are saying, it should pretty much be always locked in regardless of the frequency I select.  As it is, I very seldom am able to get it to lock in to more than one frequency in the whole range available to Tony's VIC circuit.

as i also pointed before you might be varying the pot resistor r1 (pin 11) instead of r2 (pin 12)... r1 mess around with the center frequency broadening and narrowing the bandwidth, while r2 would only changes the off set letting you chose an R1 for a more or less fix and limited bandwidth... this is handy while trying to reject signals...

I am actually not varying the gate frequency at all.  I am varying the PLL frequency using R3.  I have the gate duty cycle set so that the scope shows the PLL pulse at about 50% and the gate frequency I don't really touch.  In fact, I sometimes turn off the gate, although I usually end up losing resonance eventually when I do.  The gate is primarily meant to limit production of gas to the amount that is needed in realtime.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on October 02, 2012, 18:33:21 pm
I was talking about the frequency

in the pll r1 sets the center frequency while r2 sets the off set min frequency look the datasheet... the r3 should be the filter resistor and  r4 the damping resistor

where is  your r3 connected to? the one you vary the freq...

I would still insist your not discrimating the feedback signal by its lewel



Title: Re: My pll circuit
Post by: Login to see usernames on October 02, 2012, 19:39:55 pm
I was talking about the frequency

in the pll r1 sets the center frequency while r2 sets the off set min frequency look the datasheet... the r3 should be the filter resistor and  r4 the damping resistor

where is  your r3 connected to? the one you vary the freq...

I would still insist your not discrimating the feedback signal by its lewel

How do you explain the current drop to lowest level when the resonant indicator comes on?   See R3 on attachment.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on October 02, 2012, 21:09:54 pm
I still don't understand where your R3 is connected to.

I'm not sure, but from what i simulated it diverges in behavior... If we mean to find the self resonance of the transformer i believe mine ideas could fix... The restriction of the amps in this case would be due to many many many series of parallel resonances making the impedance gigantic, this would restrict lots of amps...
Title: Re: My pll circuit
Post by: Login to see usernames on October 02, 2012, 22:45:10 pm
I still don't understand where your R3 is connected to.

I'm not sure, but from what i simulated it diverges in behavior... If we mean to find the self resonance of the transformer i believe mine ideas could fix... The restriction of the amps in this case would be due to many many many series of parallel resonances making the impedance gigantic, this would restrict lots of amps...

I have not really looked at self resonance qualities of the transformer.  From my experiments to date, the LC resonance is what we should be looking for primarily in my opinion.

Tony posted the schematic for the VIC.  You can find it here:  http://www.globalkast.com/docs/VIC_Circuit_Production.pdf

TS
Title: Re: My pll circuit
Post by: Login to see usernames on October 02, 2012, 23:34:08 pm
like i expected is connected to pin11.... please read once more what i wrote about it if you are interested...why would you mess around with the bandwidth instead of offset?

I can only tell you more about if i could see the signals present... this light being on does not mean there is resonance... nor it may mean its locked in, it sometimes can show false lock in...

from my experiments i can tell you that i'm considering it.. .

SBS
Title: Re: My pll circuit
Post by: Login to see usernames on October 02, 2012, 23:35:40 pm
like i expected is connected to pin11.... please read once more what i wrote about it if you are interested...why would you mess around with the bandwidth instead of offset?

I can only tell you more about if i could see the signals present... this light being on does not mean there is resonance... nor it may mean its locked in, it sometimes can show false lock in...

from my experiments i can tell you that i'm considering it.. .

SBS

And as we discussed previously a few days ago, I have already changed it to pin 12!  At any rate, it may be that what I am doing is wrong.  However to date, after changing from pin 11 to pin 12 as we previously discussed, everything has been behaving exactly as I expect it would according to descriptions by Meyers.  Yes I have observed "false" lock-ins.  I have commented on that already.  Usually a "false" lock in is manifest in that the LED does not illuminate brightly, but rather it kind of fades in and out gradually.  Lock in is particularly noticed once the circuit itself not only locks in but also stays locked in at that frequency.  If it is a "false" lock in, the scanning circuit continues to scan through the frequencies.  Additionally, the lock in frequency changes based a variety of factors including cell size, water quality, coil and amount of gas being produced.  I have observed how all of these factors affect the frequency and can reproduce the results.  All the results I am getting seem to correspond to Meyer's explanations.

Most of the time I spend doing this is in actual experimentation and little documentation.  I make note of the most interesting and noteworthy results and observations here.  My interpretation of the results of course may be wrong at times.  But that is why we are here, so I appreciate your feedback.

I am regularly reviewing everything you have posted in this particular subject as to date it is one of the most productive ones I have been involved with and I appreciate your openness with your discoveries and opinions.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on October 02, 2012, 23:46:30 pm
ahh ok... nice i didn't understood that... how about the capacitor stuff?
Title: Re: My pll circuit
Post by: Login to see usernames on October 02, 2012, 23:47:22 pm
ahh ok... nice i didn't understood that... how about the capacitor stuff?

I haven't gotten that far but have it in mind.  Limited time I'm afraid.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on October 02, 2012, 23:56:21 pm
Thats nice, hope you find some time, thanks for reading and posting your results too. i appreciate that too. sorry i was a bit confuse about your progress.. i  wanted to clear thing out...  to understand better your results

sbs

Title: Re: My pll circuit
Post by: Login to see usernames on October 04, 2012, 07:43:33 am
I made a modification to the resonant scanning circuit... its much simpler and better... it now scans all the range of the pll... from 1-11volts @ 0.722Hz

also the gate circuit now from 0,7hz up to 7khz with more precision...



Title: Re: My pll circuit
Post by: Login to see usernames on October 06, 2012, 13:07:31 pm
Ts i think i see why when you lock in your current get smaller... when it lock in it maintain a fixed frequency... while scanning it sweeps the frequency so making current to flow more...

could be that?

Title: Re: My pll circuit
Post by: Login to see usernames on October 06, 2012, 18:47:02 pm
Ts i think i see why when you lock in your current get smaller... when it lock in it maintain a fixed frequency... while scanning it sweeps the frequency so making current to flow more...

could be that?

Not likely.  When manually scanning I get the same results.  Also, when auto scanning, the lock in frequency gets followed by the circuit only so far before it has to start scanning again to relock the frequency.  Fixed frequencies when scanning manually do not result in the low currents I've experienced specifically in a lock condition.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on October 06, 2012, 19:05:53 pm
It was just a thought i had here... i'm finishing my first box here can't wait anymore for testing it...

Title: Re: My pll circuit
Post by: Login to see usernames on October 06, 2012, 19:25:04 pm
It was just a thought i had here... i'm finishing my first box here can't wait anymore for testing it...

Looking forward to your report.

TS
Title: Re: My pll circuit
Post by: Login to see usernames on October 07, 2012, 18:31:32 pm
while working with the scanning circuit i found why the lock in led blinks or what it causes...

when this happens the scanning circuit will be trigered by a false lock so the vco receives a pulsing not a stable voltage so the duty cycle output of the signal get distorted... with no signal on in put...

This is only avoided by adding even more capacitance to the lock in circuit.

Title: Re: My pll circuit
Post by: Login to see usernames on October 08, 2012, 16:26:33 pm
I think i found a better usage for the 4way switches i hawe here...

My one here has 3 sets of 4 position meaning i can use 3 different functions for it to switch at the same time....

For example i could use a different capacitor for the lock in for each frequency range and so on...adding a led to indicate what range it is  being used..

or the filter capacitor...

I plan to use this two first for now... 
Title: Re: My pll circuit
Post by: Login to see usernames on October 08, 2012, 18:58:36 pm
Today it didn't acted that funny...
Title: Re: My pll circuit
Post by: Login to see usernames on October 17, 2012, 03:14:29 am
I found that the osc on led act wrong when gating 100% some times it stay light and some times low because the counter won't finish aways at low logic. So i added a modification to the circuit of the led using the gate signal from pin 5 and another transistor shorting the base of the led transistor to ground, so now it show properly if there is or not signal going out...

Title: Re: My pll circuit
Post by: Login to see usernames on October 17, 2012, 03:21:45 am
My box is now ready for testing it is really stable... also my new H bridge circuit output also works perfectly... It came out better than i expected but not as cool as the new ones upcoming...

Finally something that still works after drop it on the ground.

I'm going to start testing now!







Title: Re: My pll circuit
Post by: Login to see usernames on October 17, 2012, 13:31:05 pm
My box is now ready for testing it is really stable... also my new H bridge circuit output also works perfectly... It came out better than i expected but not as cool as the new ones upcoming...

Finally something that still works after drop it on the ground.

I'm going to start testing now!

I only drop my wife on the ground from time to time...   ;D ;D ;D ;D ;D

I know. This post is not exactly high tech quality, but heeeeeeeeeeeeeee...... i worked my bud off to get the forum all working again!

 8) 8) 8) 8) 8) 8) 8) 8) 8) 8)

Mr. Sebosfato Meyer!




Title: Re: My pll circuit
Post by: Login to see usernames on October 17, 2012, 13:36:33 pm
It generates frequency within the following ranges

1,6khz up to 19khz manually (fine tune) or auto tuning when R2 is maximum

16khz to 25khz when R2 set to min...

the bandwidth can be narrower for example going from 1,4khz up to 10khz than from 16-20kz .... raising R1

so scanning occurs within this bandwidths and intermediates config of R2 pot

also divided by 10, 100 and 1000 

so the led bliks at 1hz up to 25 hz

the gate goes from 0,5 hz up to 6,5khz approximately
0,5- 6 hz
5,6-65 hz
56-650 hz
560-6500hz

the scan circuit auto mode runs at 0,7hz scanning the all bandwidth within each half period.




Title: Re: My pll circuit
Post by: Login to see usernames on October 17, 2012, 13:49:36 pm
 :D Steve

I'm thankful to your efforts, i see your feeling good about the forum issue solved, i'm happy for that too!!! ... I get this sensation about my little box here too=) Becareful with the wife bro  8) 8) 8) 8) kkkk Mr Steve Meyer

New schematic...  new ideas... the establishment can't hold me down...

New video

this quick video show the scan and manual tuning of pll circuit at work...
Title: Re: My pll circuit
Post by: Login to see usernames on October 17, 2012, 21:57:31 pm
in that schematic those 11 pins are wrong suppose to be 12...


I just found a great feature of the box i built, it has H bridge full wave square output, or two half bridge outputs 180° de-phased... thought...

Now is time to build some new cells for testing.
Title: Re: My pll circuit
Post by: Login to see usernames on October 18, 2012, 18:58:56 pm
Hi Sebosfato
Can you share schematic of your H bridge?
thank
andy
Title: Re: My pll circuit
Post by: Login to see usernames on October 18, 2012, 20:45:26 pm
here it goes...
Title: Re: My pll circuit
Post by: Login to see usernames on October 19, 2012, 14:27:35 pm
If you want you can use a positive voltage regulator just need to connect the reference floating positive to this rail.

in this schematic Q1 Q3 and one neg diode are at the same heat sink while theres same config for Q2 Q4 and the other neg diode in another heat sink, while diodes connected to positive side sits at another heat sink...all isolated from each other..

The mosfets could be all NPN but in that case each should have its own heat sink...  this way it can be made more powerful... for it to work with only npns you need to change the position of the load resistors at the optoisolators such that the signal become inverted or simply replace the ir4427 with a ir4426 at the floating circuit...
Title: Re: My pll circuit
Post by: Login to see usernames on October 19, 2012, 16:27:39 pm
Thank you Sebosfato
andy
Title: Re: My pll circuit
Post by: Login to see usernames on October 19, 2012, 22:18:59 pm
ops incomplete info..

another change needed for using only npns is that you need a fourth transformer because each side of the bridge will require isolated inputs.. so also increase a lot complexity... also being it a npns...in each side the reference will be floating and i'm not sure if this complexity is better or not than using pnps... the floating is not at the same position too so 2 regulators must be used. the references will be the outputs of the bridge for sake of clarity, instead of the positive rail.

so to increase power add many in parallel instead of using the npns only...   

My schematic should be nice enough
you welcome
Title: Re: My pll circuit
Post by: Login to see usernames on October 21, 2012, 05:42:08 am
made some nice tests today and got a pnp mosfet and a optocoupler zapped... on the H bridge...
the scanning circuit makes a nice sound at the core junction in the audible range...

all working again... pretty nice indeed...

at 25v variac it puts out a nice 50v square wave on the oscilloscope... peak to peak...
Title: Re: My pll circuit
Post by: Login to see usernames on October 22, 2012, 17:07:56 pm
lifting the ground reference of the oscilloscope to the node between the coil and capacitor than connecting the two channels across the components makes a lysergic figures plotting XY ...

I still don't know what this mean... but at a specific frequency the forms get curly instead of straight lines..

I guess this is close to what would be resonance.. .

strangely enough i could not put this capacitor in resonance, i mean i was not able to resonate it like the other bigger cell with smaller gap in the past...

Is a very cool tool to learn the oscilloscope... wish i had one like this few years ago... 
Title: Re: My pll circuit
Post by: Login to see usernames on October 25, 2012, 04:42:48 am
today incredible results

while doing my tests here i got with a simple capacitor and inductor started testing my pll unit... i constructed a current transformer with somewhat undetermined number of turns... for my surprise it was creating more than 300v feedback it almost blew the lm318 but the circuit design is well protected... it arched to the 4001 chip...

for record the voltage applied on the H bridge was around 3v the current was around 2 amps and the  voltage across the components was kind of 400 v

well the strangest thing about it is that when i tried to get around the high voltage by loading this simple small toroid... i picked a resistor of maybe 100ohms and connected across the secondary... the resonance damped a lot...

 
Title: Re: My pll circuit
Post by: Login to see usernames on October 25, 2012, 14:12:22 pm
another great stuff is that the feed back indicator clearly indicates resonant conditions and some harmonics too... 

The only problem s that it is not locking in phase... maybe some problem with the lock in chip.. get to see

i'm using cooperatively my protoboard and the box plls to solve this problems...

i guess reflected impedance is what damped my resonance here... as the coils were air core, the single fact that this line gets into the current transformer it sees the reflected impedance of the secondary load-- basicaly as the current changes and induce a voltage in the secondary, the secondary current flowing induces a counter emf in the primary that reduces the applied emf directly... so damping resonance...



Title: Re: My pll circuit
Post by: Login to see usernames on October 25, 2012, 21:23:10 pm
I clearly see why me and many didn't succeeded yet to accomplish this stuff i for example aways started my experiments from messy environments.

Finishing this box and making sure all functions work great is just a great start but not the end. Still valid because other next experiments will come out better and easier and faster.

Now i'm working on a big cell to try some ideas... recalling stan called it an electrically isolated resonant cavity... i'm going to put all inside tubes soldered together in an ss base. With some holes around it to insert plastic stubs for centralizing and hold perfectly the outer tube.

I will make three pairs like this and three being the outer tubes soldered to the base...  why three? no reason at all...

I'm concerned about the fact that the potential is constant inside a conductive where although electric field is zero (due to a charge only in the outer tube only)... if the charge instead is applied to the inner tube there is potential and Electric field...




Title: Re: My pll circuit
Post by: Login to see usernames on October 29, 2012, 17:10:35 pm
Now i got the automatic mode all full working!!! its able to follow another frequency from other pll generator and the other is also able to maintain lock in from the first signal when inwerted, but following the auto mode...
if both plls has the same configuration it follows all the range without losing lock in!!!!!!

the ground tracks got burned during the feed back experiment so i fixed and now all works properly ...
Title: Re: My pll circuit
Post by: Login to see usernames on October 29, 2012, 17:14:52 pm
I found a way to it to better lock in in the manual tuning too.. is just required a high impedance (10 megaohm) potentiometer for the manual button with respective 1 megaohms resistors.. and a filter consisting of 100nf capacitor in parallel with it having a 100k resistor from pin 13 to it... or conecting this node straight to pin 9..

this way when close to the lock in the capacitor impedance path will be smaller than the pot so it can adjust itself... well thats the idea.. . maybe not really needed because automode works just great... any way  when i get more components i will try this one..
Title: Re: My pll circuit
Post by: Login to see usernames on October 30, 2012, 05:16:23 am
I dig more tests today.. i made the modification proposed using the same pot i got here 22k and worked.. .i can finely tune to the reference frequency and adjust the phase relationship too!! would be better with a higher resistance pot anyways ...

I added a 100nf cap to the filter circuit so now it works properly in all ranges...

its able to lock in phase within all the range of operation when in auto mode.. but at the lower range it suffer a bit making somewhat strange waweforms up to the point R2 is set to a good position... maybe the filter cap should be increased..



Title: New test cell
Post by: Login to see usernames on November 05, 2012, 20:59:04 pm
here it goes.. o-rings rocks

no leaks no problems =)
Title: Re: My pll circuit
Post by: Login to see usernames on November 07, 2012, 09:18:37 am
Nice dude!
Title: Re: My pll circuit
Post by: Login to see usernames on November 07, 2012, 17:52:23 pm
Happy you like it. it was done for me by professionals with big machinery... the cool thing is that it can be easy disassembly to work inside if needed.

each tube has around 190nf in air... so around 16nf with water...